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information furnished by analog devices is be lieved to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or oth- erwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? 2004 analog devices, inc. all rights reserved. ad9851 cmos 180 mhz dds/dac synthesizer features 180 mhz clock rate with selectable 6 reference clock multiplier on-chip high performance 10-bit dac and high speed comparator with hysteresis sfdr >43 db @ 70 mhz a out 32-bit frequency tuning word simplif ed control interface: parallel or serial asynchronous loading format 5-bit phase modulation and offset capability comparator jitter <80 ps p-p @ 20 mhz 2.7 v to 5.25 v single-supply operation low power: 555 mw @ 180 mhz power-down function, 4 mw @ 2.7 v ultrasmall 28-lead ssop packaging applications frequency/phase-agile sine wave synthesis clock recovery and locking circuitry for digital communications digitally controlled adc encode generator agile local oscillator applications in communications quadrature oscillator cw, am, fm, fsk, msk mode transmitter functional block diagram 32-bit tuning word phase and control words frequency/phase data register data input register 10-bit dac dac r set analog out analog in clock out clock out high speed dds frequency update/data register reset word load clock master reset ref clock in 6 refclk multiplier comparator serial load 1 bit 40 loads pa rallel load 8 bits 5 loads frequency, phase and control data input ad9851 +v s gnd general description the ad9851 is a highly integrated device that uses advanced dds technology, coupled with an internal high speed, high performance d/a converter, and comparator, to form a dig i tal ly programmable frequency synthesizer and clock generator func- tion. when referenced to an accurate clock source, the ad9851 generates a stable frequency and phase-programmable digitized analog output sine wave. this sine wave can be used directly as a frequency source, or internally converted to a square wave for agile-clock generator applications. the ad9851s innovative high speed dds core accepts a 32-bit frequency tuning word, which results in an output tuning res o lu tion of approximately 0.04 hz with a 180 mhz system clock. the ad9851 con tains a unique 6 refclk multiplier circuit that eliminates the need for a high speed reference oscillator. the 6 refclk multiplier has min i mal impact on sfdr and phase noise char- ac ter is tics. the ad9851 provides f ve bits of programmable phase mod u la tion resolution to enable phase shifting of its output in in cre ments of 11.25. the ad9851 contains an internal high speed comparator that can be conf gured to accept the (externally) f ltered output of the dac to generate a low jitter output pulse. the frequency tuning, control, and phase modulation words are asynchronously loaded into the ad9851 via a parallel or serial loading format. the parallel load format consists of f ve it er a tive loads of an 8-bit control word (byte). the f rst 8-bit byte controls output phase, 6 refclk multiplier, power-down enable and loading for mat; the remaining bytes comprise the 32-bit frequency tuning word. serial loading is accomplished via a 40-bit serial data stream entering through one of the parallel input bus lines. the ad9851 uses advanced cmos technology to provide this break- through level of functionality on just 555 mw of power dissipation (5 v supply), at the maximum clock rate of 180 mhz. the ad9851 is available in a space-saving 28-lead ssop, surface-mount package that is pin-for-pin compatible with the popular ad9850 125 mhz dds. it is specif ed to operate over the extended industrial temperature range of C40c to +85c at >3.0 v supply voltage. below 3.0 v, the specif cations apply over the commercial temperature range of 0c to 85c. rev. d
C2 C ad9851Cspecifications (v s 1 = 5 v 5%, r set = 3.9 k , 6 refclk multiplier disabled, external ref er ence clock = 180 mhz, except as noted.) test ad9851brs p arameter temp level min typ max unit clock input characteristics frequency range (6 refclk multiplier disabled) 5.0 v supply full iv 1 180 mhz 3.3 v supply full iv 1 125 mhz 2.7 v supply 0c to 85c iv 1 100 mhz frequency range (6 refclk multiplier enabled) 5.0 v supply full iv 5 30 mhz 3.3 v supply full iv 5 20.83 mhz 2.7 v supply 0c to 85c iv 5 16.66 mhz duty cycle full iv 45 60 % duty cycle (6 refclk multiplier enabled) full iv 35 65 % input resistance 25c v 1 m minimum switching thresholds 2 logic 1, 5.0 v supply 25c iv 3.5 v logic 1, 3.3 v supply 25c iv 2.3 v logic 0, 5.0 v supply 25c iv 1.5 v logic 0, 3.3 v supply 25c iv 1 v dac output characteristics full-scale output current 25c iv 5 10 20 ma gain error 25c i C10 +10 % fs output offset 25c i 10 a differential nonlinearity 25c i 0.75 lsb integral nonlinearity 25c i 1 lsb residual phase noise, 5.2 mhz, 1 khz offset pll on 25c v C125 dbc/hz pll off 25c v C132 dbc/hz output impedance 25c v 120 k voltage com pli ance range 25c i C0.5 +1.5 v wideband spu ri ous-free dynamic range 1.1 mhz analog out (dc to 72 mhz) 25c iv 60 64 dbc 20.1 mhz an a log out (dc to 72 mhz) 25c iv 51 53 dbc 40.1 mhz analog out (dc to 72 mhz) 25c iv 51 55 dbc 50.1 mhz an a log out (dc to 72 mhz) 25c iv 46 53 dbc 70.1 mhz analog out (dc to 72 mhz) 25c iv 42 43 dbc narrowband spurious-free dynamic range 1.1 mhz (50 khz) 25c v 85 dbc 1.1 mhz (200 khz) 25c v 80 dbc 40.1 mhz (50 khz) 25c v 85 dbc 40.1 mhz (200 khz) 25c v 80 dbc 70.1 mhz (50 khz) 25c v 85 dbc 70.1 mhz (200 khz) 25c v 73 dbc comparator input characteristics input capacitance 25c v 3 pf input re sis tance 25c iv 500 k input bias current 25c i 12 a input voltage range 25c iv 0 5 v comparator output characteristics logic 1 voltage 5 v supply 25c vi 4.8 v logic 1 voltage 3.3 v supply 25c vi 3.1 v logic 1 voltage 2.7 v supply 25c vi 2.3 v logic 0 voltage 25c vi +0.4 v continuous output current 25c iv 20 ma hysteresis 25c iv 10 mv propagation delay 25c iv 7 ns toggle frequency (1 v p-p input sine wave) 25c iv 200 mhz rise/fall time, 15 pf output load 25c iv 7 ns output jitter (p-p) 3 25c iv 80 ps (p-p) clock output char ac ter is tics output jitter (clock generator conf guration, 40 mhz 1 v p-p input sine wave) 25c v 250 ps (p-p) clock output duty cycle full iv 50 10 % rev. d
ad9851 C3 C test ad9851brs parameter temp level min typ max unit timing characteristics 4 t wh , t wl (w_clk min pulse width high/low) wl (w_clk min pulse width high/lo w) wl full iv 3.5 ns t ds , t dh (data to w_clk setup and hold times) full iv 3.5 ns t fh , t fl (fq_ud min pulse width high/low) fl (fq_ud min pulse width high/lo w) fl full iv 7 ns t cd (refclk delay after fq_ud) 5 full iv 3.5 ns t fd (fq_ud min delay after w_clk) full iv 7 ns t cf (out put latency from fq_ud) frequency change full iv 18 sysclk cycles phase change full iv 13 sysclk cycles t rh (clkin delay after reset rising edge) full iv 3.5 ns t rl (reset falling edge after clkin) rl (reset f alling edge after clkin) rl full iv 3.5 ns t rr (recovery from reset) rr (reco v er y from reset) rr full iv 2 sysclk cycles t rs (min i mum re set width) full iv 5 sysclk cycles t ol (reset output latency) ol (reset output la tenc y) ol full iv 13 sysclk cycles wake-up time from power-down mode 6 25c v 5 s cmos logic inputs logic 1 voltage, 5 v supply 25c i 3.5 v logic 1 voltage, 3.3 v supply 25c iv 2.4 v logic 1 voltage, 2.7 v supply 25c iv 2.0 v logic 0 voltage 25c iv 0.8 v logic 1 current 25c i 12 a logic 0 current 25c i 12 a rise/fall time 25c iv 100 ns input capacitance 25c v 3 pf power supply v s 6 current @: 62.5 mhz clock, 2.7 v supply 25c vi 30 35 ma 100 mhz clock, 2.7 v supply 25c vi 40 50 ma 62.5 mhz clock, 3.3 v supply 25c vi 35 45 ma 125 mhz clock, 3.3 v supply 25c vi 55 70 ma 62.5 mhz clock, 5 v supply 25c vi 50 65 ma 125 mhz clock, 5 v supply 25c vi 70 90 ma 180 mhz clock, 5 v supply 25c vi 110 130 ma power dissipation @ : 62.5 mhz clock, 5 v supply 25c vi 250 325 mw 62.5 mhz clock, 3.3 v supply 25c vi 115 150 mw 62.5 mhz clock, 2.7 v supply 25c vi 85 95 mw 100 mhz clock, 2.7 v supply 25c vi 110 135 mw 125 mhz clock, 5 v supply 25c vi 365 450 mw 125 mhz clock, 3.3 v supply 25c vi 180 230 mw 180 mhz clock, 5 v supply 25c vi 555 650 mw p diss power-down mode @: 5 v supply 25c vi 17 55 mw 2.7 v supply 25c vi 4 20 mw notes 1 +v s collectively refers to the positive voltages applied to dvdd, pvcc, and avdd. voltages applied to these pins should be of the same po ten tial. 2 indicates the minimum signal levels required to reliably clock the device at the indicated supply voltages. this specif es the p-p signal level and dc offset needed when the clocking signal is not of cmos/ttl origin, i.e., a sine wave with 0 v dc offset. 3 the comparators jitter contribution to any input signal. this is the minimum jitter on the outputs that can be expected from an ideal input. considerably more output jitter is seen when nonideal input signals are presented to the compara tor inputs. nonideal characteristics include the presence of extraneous, nonharmonic signals (spurs, noise), slower slew rate, and low comparator overdrive. 4 timing of input signals fq_ud, wclk, reset are asynchronous to the reference clock; however, the presence of a reference clock is required to implement those functions. in the absence of a reference clock, the ad9851 automatically enters power-down mode rendering the ic, including the comparator, inoperable until a refer- ence clock is restored. very high speed updates of frequency/phase word will require fq_ud and wclk to be externally synchronized with the ex ter nal reference clock to ensure proper timing. 5 not applicable when 6 refclk multiplier is engaged. 6 assumes no capacitive load on dacbp (pin 17). specif cations subject to change without notice. rev. d
ad9851 C4 C caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily ac cu mu late on the human body and test equipment and can discharge without detection. although the ad9851 features proprietary esd pro tec tion circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd pre cau tions are rec om mend ed to avoid per for mance deg ra da tion or loss of functionality. application note: users are cautioned not to apply digital input signals prior to power-up of this device. doing so may result in a latch-up condition. absolute maximum ratings * maximum junction temperature . . . . . . . . . . . . . . . . . . . 150c storage tem per a ture . . . . . . . . . . . . . . . . . . . C65c to +150c v s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 v operating temperature . . . . . . . . . . . . . . . . . . . C40c to +85c digital inputs . . . . . . . . . . . . . . . . . . . . . . C0.7 v to +v s + 0.7 v lead temperature (10 sec) soldering . . . . . . . . . . . . . . . . 300c digital output current . . . . . . . . . . . . . . . . . . . . . . . . . . 30 ma ssop ja thermal impedance . . . . . . . . . . . . . . . . . . . 82c/w dac output current . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 ma * absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. functional operability under any of these conditions is not necessarily implied. exposure of absolute maximum rating conditions for extended periods of time may affect device reliability. explanation of test levels test level i C 100% production tested. iii C sample tested only. iv C pa ram e ter is guaranteed by design and char ac ter iza tion testing. v C parameter is a typical value only. vi C devices are 100% pro duc tion tested at 25c and guar an - teed by design and characterization testing for in dus tri al operating temperature range. ordering guide model temperature range package description package option ad9851brs C40c to +85c shrink small outline (ssop) rs-28 ad9851brsrl C40c to +85c shrink small outline (ssop) rs-28 ad9851/cgpcb evaluation board clock generator ad9851/fspcb evaluation board frequency synthesizer rev. d
ad9851 C5 C p in function descriptions pin no. mnemonic function 4C1, d0Cd7 8-bit data input. the data port for loading the 32-bit frequency and 8-bit phase/control words. d7 = msb; 28C25 d0 = lsb. d7, pin 25, also serves as the input pin for 40-bit serial data word. 5 pgnd 6 refclk multiplier ground connection. 6 pvcc 6 refclk multiplier positive supply voltage pin. 7 w_clk word load clock. rising edge loads the parallel or serial frequency/phase/control words asynchronously into the 40-bit input register. 8 fq_ud frequency update. a rising edge asynchronously transfers the contents of the 40-bit input register to be acted upon by the dds core. fq_ud should be issued when the contents of the input register are known to contain only valid, allowable data. 9 refclock reference clock input. cmos/ttl-level pulse train, direct or via the 6 refclk multiplier. in direct mode, this is also the system clock. if the 6 refclk multiplier is engaged, then the out put of the multiplier is the sys tem clock. the rising edge of the system clock initiates op er a tions. 10, 19 agnd analog ground. the ground return for the analog circuitry (dac and comparator). 11, 18 avdd positive supply voltage for analog circuitry (dac and comparator, pin 18) and bandgap volt age ref er ence, pin 11. 12 r set the dacs external r set connectionnominally a 3.92 k resistor to ground for 10 ma out. this sets the dac full-scale output current available from iout and ioutb. r set = 39.93/iout. 13 voutn voltage output negative. the comparators complementary cmos logic level output. 14 voutp voltage output positive. the comparators true cmos logic level output. 15 vinn voltage input negative. the comparators inverting input. 16 vinp voltage input positive. the comparators noninverting input. 17 dacbp dac bypass connection. this is the dac voltage reference bypass connection normally nc (no connect) for optimum sfdr performance. 20 ioutb the complementary dac output with same characteristics as iout except that ioutb = (full-scale outputCiout) . output load should equal that of iout for best sfdr performance. 21 iout the true output of the balanced dac. current is sourcing and requires current-to-voltage conversion, usually a resistor or transformer referenced to gnd. iout = (full-scale outputCioutb). 22 reset master reset pin; active high; clears dds accumulator and phase offset register to achieve 0 hz and 0 output phase. sets programming to parallel mode and disengages the 6 refclk multiplier. reset does not clear the 40-bit input reg is ter. on pow er-up, as sert ing re set should be the f rst pri or i ty before pro- gramming com menc es. 23 dvdd positive supply voltage pin for digital circuitry. 24 dgnd dig i tal ground. the ground return pin for the digital circuitry. pin configuration top view (not to scale) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ad9851 voutp voutn r set avdd agnd refclock fq ud d3 d2 d1 lsb d0 pvcc pgnd vinn vin p dacbp avdd agnd ioutb iout d4 d5 d6 d7 msb/serial load reset dvdd dgnd w clk rev. d
C6 C ad9851Ctypical performance characteristics 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 0h z start 72mhz stop 7.2mhz/ rbw = 5khz vbw = 5khz swt = 7.2s rf att = 20db ref lvl = C7dbm 2ap tpc 1. wideband (dc to 72 mhz) output sfdr for a 1.1 mhz fundamental output signal. system clock = 180 mhz (6 refclk multiplier engaged), v s v s v = 5 v. s = 5 v . s 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 2ap 0h z start 72mhz stop 7.2mhz/ rbw = 5khz vbw = 5khz swt = 7.2s rf att = 20db ref lvl = C7dbm tpc 2. wideband (dc to 72 mhz) output sfdr for a 40.1 mhz fundamental output signal. system clock = 180 mhz (6 refclk multiplier engaged), v s v s v = 5 v. s = 5 v . s 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 2ap 0h z start 72mhz stop 7.2mhz/ rbw = 5khz vbw = 5khz swt = 7.2s rf att = 20db ref lvl = C7dbm tpc 3. wideband (dc to 72 mhz) output sfdr for a 70.1 mhz fundamental output signal. system clock = 180 mhz (6 refclk multiplier engaged), v s v s v = 5 v. s = 5 v . s 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 2ap 1.1mhz center 200khz span 20khz/ rbw = 300hz vbw = 300hz swt = 11.5s rf att = 20db ref lvl = C7dbm tpc 4. narrowband (1.1 0.1 mhz) output sfdr for a 1.1 mhz fundamental output signal. system clock =180 mhz (6 refclk multiplier engaged), v s v s v = 5 v. s = 5 v . s 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 2ap 40.1mhz center 200khz span 20khz/ rbw = 300hz vbw = 300hz swt = 11.5s rf att = 20db ref lvl = C7dbm tpc 5. narrowband (40.1 0.1 mhz) output sfdr for a 40.1 mhz fundamental output signal. system clock = 180 mhz (6 refclk multiplier engaged), v s v s v = 5 v. s = 5 v . s 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 2ap 70.1mhz center 200khz span 20khz/ rbw = 300hz vbw = 300hz swt = 11.5s rf att = 20db ref lvl = C7dbm tpc 6. narrowband (70.1 0.1 mhz) output sfdr for a 70.1 mhz fundamental output signal. system clock = 180 mhz (6 refclk multiplier engaged), v s v s v = 5 v. s = 5 v . s rev. d
ad9851 C7 C 1 ch1 200mv t [ ] tek run 4.00gs/s sample m 12.5ns ch 1 C200mv d 200ps runs after : 208ps @ : 1.940ns tpc 7. typical cmos comparator p-p output jitter with the ad9851 conf gured as a clock generator, dds f out the ad9851 conf gured as a clock generator, dds f o u t the ad9851 conf gured as a clock generator, dds f = out = out 10.1 mhz, v s 10.1 mhz, v s 10.1 mhz, v = 5 v, system clock = 180 mhz, 70 mhz lpf. s = 5 v , system cloc k = 1 80 mhz, 70 mhz lpf . s graph details the center portion of a rising edge with scope in delayed trigger mode, 200 ps/div. cursors show 208 ps p-p jitter. 1 ch1 200mv t [ ] tek run 4.00gs/s sample m 12.5ns ch 1 C200mv d 200ps runs after : 204ps @ : 3.672ns tpc 8. typical cmos comparator p-p output jitter with the ad9851 conf gured as a clock generator, dds f out ad9851 conf gured as a clock generator, dds f o u t ad9851 conf gured as a clock generator, dds f = 40.1 mhz, out = 4 0 . 1 m h z , out v s v s v = 5 v, system clock = 180 mhz, 70 mhz lpf. graph details s = 5 v , s y s t e m c l o c k = 1 8 0 m h z , 7 0 m h z l p f . g r a p h d e t a i l s s the center portion of a rising edge with scope in delayed trigger mode, 200 ps/div. cur sors show 204 ps p-p jitter. 1 ch1 200mv t [ ] tek run 4.00gs/s sample : 280ps @ : 2.668ns m 12.5ns ch 1 C200mv d 200ps runs after tpc 9. typical cmos comparator p-p output jitter with the ad9851 conf gured as a clock generator, dds f out generator, dds f out generator, dds f = 70.1 mhz, v out = 70.1 mhz, v out s = 70.1 mhz, v s = 70.1 mhz, v = 5 v, system s = 5 v, system s clock = 180 mhz, 70 mhz lpf. graph details the center portion of a rising edge with scope in delayed trigger mode, 200 ps/div. cur sors show 280 ps p-p jitter. frequency offset C hz C145 100 magnitude C C dbc/hz 1k 10k 100k C135 C130 C125 C120 C115 C100 ad9851 phase noise C140 tpc 10. output phase noise (5.2 mhz a out ), 6 out ), 6 out refclk multiplier enabled, system clock = 180 mhz, reference clock = 30 mhz rev. d
ad9851 C8 C frequency offset C hz C155 100 magnitude C C dbc/hz 1k 10k 100k C145 C140 C135 C130 C125 C120 ad9851 residual phase noise C150 tpc 11. output residual phase noise (5.2 mhz a out ), 6 out ), 6 out refclk multiplier disabled, system clock = 180 mhz, ref- erence clock = 180 mhz system clock frequency C mhz 45 10 sfdr C C dbc 20 40 60 80 100 120 140 160 180 50 55 60 65 70 75 v s = +3.3v v s = +5v fundamental output = system clock/3 tpc 12. spurious-free dynamic range (sfdr) is gen er al ly a function of the dac analog output frequency. an a log output frequencies of 1/3 the system clock rate are consid- ered worst case. plotted below are typical worst case sfdr numbers for various system clock rates. 1 ch1 100mv t [ ] tek stop 2.50gs/s 22 acgs : 2.0ns @ : 105.2ns c1 rise 2.03ns m 20.0ns ch 1 252mv d 5.00ns runs after tpc 13. comparator rise time, 15 pf load 1 ch1 100mv t [ ] tek stop 2.50gs/s 2227 acgs : 2.3ns @ : 103.6ns c1 fall 2.33ns m 20.0ns ch 1 252mv d 5.00ns runs after tpc 14. comparator fall time, 15 pf load analog output frequency C mhz 30 10 supply current C ma 20 30 40 50 60 0 7 0 50 70 80 90 110 120 v s = +3.3v v s = +5v 100 60 40 tpc 1 5. supply cur rent variation with analog output frequency at 180 mhz system clock (upper trace) and 125 mhz system clock (lower trace) system clock C mhz 0 140 supply current C ma 20 40 60 100 80 120 0 20 40 60 80 100 120 v s = +3.3v v s = +5v 160 180 tpc 1 6. supply cur rent variation with system clock frequency rev. d
ad9851 C9 C maximum dac i out C ma 40 5 sfdr C C dbc 10 15 20 45 50 55 60 65 70 1.1mhz 40.1mhz 70.1mhz tpc 17. effect of dac maximum output current on wideband (0 to 72 mhz) sfdr at three representa- tive dac output frequencies: 1.1 mhz, 40.1 mhz, and 70.1 mhz. v s and 70.1 mhz. v s and 70.1 mhz. v = 5 v, 180 mhz system clock (6 s = 5 v , 1 80 mhz system cloc k (6 s refclk multiplier dis abled). currents are set using appropriate values of r set . set . set input frequency C mhz 0 0 p-p amplitude C mv 20 40 60 80 100 120 140 160 100 200 300 400 500 600 v s = +3.3v v s = +5v tpc 18. minimum p-p input signal needed to tog- gle the ad9851 comparator output. comparator input is a sine wave compared with a f xed volt- age threshold. use this data in addition to sin(x)/x rolloff and any f lter losses to determine whether adequate signal is being presented to the ad9851 comparator. rev. d
ad9851 C10 C iout and ioutb are equally loaded with 100 . two 100 k resistors sample each output and average the two volt ag es. the result is f ltered with the 470 pf ca pac i tor and ap plied to one comparator input as a dc switching threshold. the f ltered dac sine wave output is applied to the other com par a tor input. the comparator will tog gle with nearly 50% duty cycle as the sine wave al ter nate ly traverses the center point threshold. ad9851 dds reference clock if frequency in filter filter tuning wor d rf frequency out figure 3. f requency/phase-agile l ocal oscillator for frequency mixing/multiplying filter phase comparator divide-by-n loop filter vco ad9851 dds reference clock tuning word rf frequency out figure 4. frequency/phase-agile reference for pll phas e comparator loop filter vc o ad9851 dds reference clock tuning word rf frequency out filter ref clk in programmabl e divide-by-n function (where n = 2 32 / t uning word) figure 5. digitally programmable divide-by-n function in pll ad9851 dds fm rf output adsp-2181 dsp processor adsp-2181 bus input/ output decode logic 8-bit data bus ad1847 stereo codec l & r audio in ref osc dac out ad9851/fspcb evaluation board ez-kit lite dsp figure 6. high quality, all digital rf frequency mod u la tion high quality, all digital rf frequency modulation generation with the adsp-2181 dsp and the ad9851 dds is well documented in analog devices application note an-543. it uses an image of the dds output as il lus trat ed in figure 8. i/q mixer and low-pass filter i q ad9059 dual 8-bit adc 8 8 digital demodulator adc encode agc 32 chip/symbol /pn ra te da ta adc clock frequency locked to tx chip/symbol/pn rate 180mhz or 30mhz reference clock rx baseband digital data out rx rf in vca ad9851 clock generator figure 1. chip rate clock generator application in a spread spectrum receiver microprocessor or microcontroller data bus 180mhz or 30mhz reference clock 8-bit parallel data, or 1-bit 40 serial data, reset, w clk and fq ud iout 100k 100k 470p f 100 ioutb r set 3.9k cmos output s qoutb qout low-pass filter 7th order elliptical 70mhz low pass 200 impedance 200 voltage here = center point of sine wave (0.5v typically) using passive averaging circuit 0 to 1v p-p sine wave ad9851 200 figure 2. basic clock generator conf guration rev. d
ad9851 C11 C ref clock 90 phase differenc e 8-bit data bus fq ud reset w clk ad9851 #2 iout ad9851 #1 w clk fq ud reset iout reset fq ud reset fq ud w clk #2 w clk #1 microprocessor or microcontroller w clk #2 w clk #1 figure 7. application showing synchronization of two ad9851 ddss to form a quadrature oscillator after a common reset command is issued, separate w_clks allow independent programming of each ad9851 40-bit input reg- ister via the 8-bit data bus or serial input pin. a common fq_ud pulse is issued after programming is completed to simultaneously engage both oscillators at their specif ed fre quen cy and phase. ad9851 iout 30mhz clock bandpass filter 50 50 fundamental f clk image f c C f o image f c + f o amplitude 60 120 180 240 frequency C mhz 240 frequency C mhz image f c + f o bandpass filter amplitude 6 amplifier 240mhz ad9851 spectrum final output spectrum figure 8. deriving a high frequency output signal from the ad9851 by using an alias or image signal the differential dac output connection in figure 9 enables reduction of com mon-mode signals and allows highly reactive f lters to be driv en without a f lter input termination resistor (see above single-ended example, figure 8). a 6 db power advantage is obtained at the f lter output as compared with the single-ended example, since the f lter need not be doubly terminated. reference clock filter differential transformer coupled output 50 1:1 transformer i.e., mini-circuits t1C1t 50 ad9851 dds 21 20 figure 9. differential dac output connection for re duc tion of common-mode signals the ad9851 r set input is driven by an external dac (figure 10) set i n p u t i s d r i v e n b y a n e x t e r n a l d a c ( f i g u r e 1 0 ) set to provide amplitude modulation or f xed, digital am pli tude con trol of the dac output current. full description of this ap pli ca tion is found as a technical note in the ad9851 data sheet under related in for ma tion. an analog devices' application note for the ad9850, an- 423, describes another method of am pli tude control using an en hance ment mode mosfet that is equally applicable to the ad9851. note: if the 6 refclk multiplier of the ad9851 is en gaged, the 125 mhz clock ing source shown in figure 10 can be re duced by a factor of six. ad9851 dds differentia l transformer coupled output 50 1:1 transformer 50 iout iout r set +5v 21 20 12 9 4k 200 330 +5v 20ma max 10-bit da c ad9731 +5v C5v 125mhz 10 bits data generator e.g., dg-2020 computer control data figure 10. the ad9851 rset input being driven by an external dac rev. d
ad9851 C12 C theory of operation and application the ad9851 uses direct digital synthesis (dds) technology, in the form of a nu mer i cal ly controlled oscillator (nco), to gen er ate a frequency/phase-agile sine wave. the digital sine wave is converted to analog form via an internal 10-bit high speed d/a converter. an on-board high speed comparator is provided to translate the analog sine wave into a low-jitter ttl/cmos-compatible output square wave. dds technol- ogy is an in no va tive circuit architecture that allows fast and precise ma nip u la tion of its output word, under full digital con- trol. dds also enables very high resolution in the incremental se lec tion of output fre quen cy. the ad9851 allows an output fre quen cy resolution of approximately 0.04 hz at an 180 msps clock rate with the option of directly using the reference clock or by engaging the 6 refclk multiplier. the ad9851s out- put waveform is phase-con tin u ous from one output fre quen cy change to another. the basic functional block diagram and signal f ow of the ad9851 conf gured as a clock generator is shown in figure 11. the dds circuitry is basically a digital frequency divider func tion whose incremental resolution is determined by the fre quen cy of the system clock, and n (number of bits in the tuning word). the phase accumulator is a variable-modulus counter that in cre ments the number stored in it each time it receives a clock pulse. when the counter reaches full-scale it wraps around, making the phase accumulators output phase-con tin u ous. the frequency tuning word sets the modulus of the counter, which effectively determines the size of the increment ( phase) that will be added to the value in the phase accumulator on the next clock pulse. the larger the added increment, the faster the accumulator wraps around, which results in a higher output frequency. the ad9851 uses an innovative and proprietary angle ro ta tion algorithm that mathematically converts the 14-bit trun cat ed value of the 32-bit phase accumulator to the 10-bit quan tized amplitude that is passed to the dac. this unique algorithm uses a much-reduced rom look-up table and dsp to perform this func- tion. this contributes to the small size and low power dissipation of the ad9851. the relationship between the output frequency, system clock, and tuning word of the ad9851 is determined by the ex pres sion: f out f out f = ( out = ( out = ( = ( phase system clock)/ 2 32 where phase = decimal value of 32-bit frequency tuning word. system clock = direct input reference clock (in mhz) or 6 the input clock (in mhz) if the 6 refclk multiplier is engaged. f out f out f = frequency of the output signal in mhz. out = frequenc y of the output signal in mhz. out the digital sine wave output of the dds core drives the in ter nal high speed 10-bit d/a converter that will construct the sine wave in analog form. this dac has been op ti mized for dy nam ic per- formance and low glitch energy, which results in the low spurious and jitter performance of the ad9851. the dac can be operated in either the single-ended (figures 2 and 8) or dif fer en tial output conf guration (figures 9 and 10). dac out put current and r set values are determined using the fol low ing expressions: i out i out i = 39.93/ out = 39.93/ out r set r set = 39.93/ set = 39.93/ set i out i out i since the output of the ad9851 is a sampled signal, its output spectrum follows the nyquist sampling theorem. specif cally, its output spectrum contains the fundamental plus aliased sig- nals (images) that occur at integer multiples of the system clock frequency the selected output frequency. a graphical rep re - sen ta tion of the sampled spectrum, with aliased images, is shown in figure 12. normal usable bandwidth is considered to extend from dc to 1/2 the system clock. clock out amplitude/sine conv algorithm phase accumulator dds circuitry d/a converter lp comparator n reference clock tuning word specifies output frequency as a fraction of ref clock frequency in digita l domain figure 1 1 . basic dds bloc k diagram and signal flow of ad9851 120mhz 2nd image f out f c +f o 2f c Cf o 2f c +f o 3f c Cf o 180mhz 3rd image 220mhz 4th image 280mhz 5th image 80mhz 1st image 20mhz 0h z (dc) f c f c Cf o sin (x) / envelope = ( )f /f c 100mhz system clock frequency signal amplitude figure 12. output spectrum of a sampled sin(x)/x signal rev. d
ad9851 C13 C in the example shown in figure 12, the system clock is 100 mhz and the output frequency is set to 20 mhz. as can be seen, the aliased images are very prominent and of a relatively high energy level as determined by the sin(x)/x rolloff of the quantized d/a converter output. in fact, depending on the f/system clock re la tion ship, the f rst aliased image can equal the fun da men tal am pli tude (when f out am pli tude (when f out am pli tude (when f = 1/2 system clock). a low-pass f lter is gen er al ly placed between the output of the d/a converter and the input of the comparator to suppress the jitter-producing effects of nonhar mon i cal ly related aliased images and other spurious signals. consideration must be given to the relationship of the selected output frequency, the system clock frequency, and alias fre quen cies to avoid unwanted output anomalies. images need not be thought of as useless by-products of a dac. in fact, with bandpass f ltering around an image and some amount of post-f lter amplif cation, the image can become the primary output signal (see figure 8). since images are not har mon ics, they retain a 1:1 frequency relationship to the fun- da men tal output. that is, if the fundamental is shifted 1 khz, then the image is also shifted 1 khz. this relationship accounts for the frequency stability of an image, which is iden ti cal to that of the fundamental. users should recognize that the lower im age of an image pair surrounding an integer multiple of the system clock will move in a direction opposite to that of the fun da - men tal. images of an image pair located above an integer mul ti ple of the system clock will move in the same direction as a fundamen- tal move ment. the frequency band where images exist is much richer in spu- ri ous signals and, therefore, more hostile in terms of sfdr. users of this technique should empirically determine what fre- quencies are usable if their sfdr requirements are demanding. a good rule-of-thumb for applying the ad9851 as a clock gen- erator is to limit the fundamental output frequency to 40% of reference clock frequency to avoid generating aliased signals that are too close to the output band of interest (generally dc highest selected output frequency) to be f ltered. this practice will ease the complexity and cost of the external f lter re quire - ment for the clock generator application. the reference clock input of the ad9851 has a minimum lim i - ta tion of 1 mhz without 6 refclk multiplier engaged and 5 mhz with multiplier engaged. the device has internal cir cuit ry that senses when the clock rate has dropped below the minimum and au to mat i cal ly places itself in the power-down mode. in this mode, the on-chip comparator is also disabled. this is im por tant information for those who may wish to use the on-chip compara- tor for purposes other than squaring the dds sine wave output. when the clock frequency returns above the min i mum threshold, the device resumes normal operation after 5 s (typ i cal ly). this shutdown mode prevents excessive current leakage in the dynamic registers of the device. the impact of reference clock phase noise in dds systems is ac tu al ly reduced, since the dds output is the result of a division of the input frequency. the amount of apparent phase noise re duc tion, expressed in db, is found using 20 log f out re duc tion, expressed in db, is found using 20 log f o u t re duc tion, expressed in db, is found using 20 log f /f clk /f c l k /f , where f out where f o u t where f is the fundamental dds output frequency and f clk is the fundamental dds output frequency and f c l k is the fundamental dds output frequency and f is clk i s clk the system clock frequency. from this standpoint, using the high- est system clock input fre quen cy makes good sense in re duc ing the effects of reference clock phase noise contribution to the output signals overall phase noise. as an example, an os cil la tor with C100 dbc phase noise operating at 180 mhz would appear as a C125 db con tri bu tion to dds overall phase noise for a 10 mhz output. en gag ing the 6 refclk multiplier has gen er al ly been found to increase overall output phase noise. this increase is due to the inherent 6 (15.5 db) phase gain transfer function of the 6 refclk multiplier, as well as noise gen er at ed internally by the clock multiplier circuit. by using a low phase noise reference clock input to the ad9851, users can be assured of better than C100 dbc/hz phase noise performance for output frequencies up to 50 mhz at offsets from 1 khz to 100 khz. programming the ad9851 the ad9851 contains a 40-bit register that stores the 32-bit frequency control word, the 5-bit phase modulation word, 6 refclk multiplier, enable, and the power-down func- tion. this register can be loaded in parallel or serial mode. a logic high engages functions; for example, to power-down the ic (sleep mode), a logic high must be programmed in that bit lo ca tion. those users who are familiar with the ad9850 dds will f nd only a slight change in programming the ad9851, spe cif cal ly, data[0] of w0 (parallel load) and w32 (serial load) now contains a 6 refclk multiplier enable bit that needs to be set high to enable or low to disable the internal reference clock multiplier. note: setting data[1] high in programming word w0 (par al lel mode) or word w33 high in serial mode is not allowed (see tables i and iii). this bit controls a factory test mode that will cause abnormal operation in the ad9851 if set high. if er ro - ne ous ly en tered (as evidenced by pin 2 changing from an input pin to an output signal), an exit is provided by asserting reset. unintentional entry to the factory test mode can occur if an fq_ud pulse is sent after initial pow er-up and re set of the ad9851. since reset does not clear the 40-bit input register, this will transfer the random power-up values of the input register to the dds core. the random values may invoke the factory test mode or power-down mode. never issue an fq_ud command if the 40-bit input register contents are unknown. in the default parallel load mode, the 40-bit input register is load ed using an 8-bit bus. w_clk is used to load the register in f ve iterations of eight bytes. the rising edge of fq_ud transfers the contents of the register into the device to be acted upon and resets the word address pointer to w0. subsequent w_clk rising edges load 8-bit data, starting at w0 and then move the word pointer to the next word. after w0 through w4 are loaded, additional w_clk edges are ignored until either a reset is asserted or an fq_ud rising edge resets the address pointer to w0 in prepara- tion for the next 8-bit load. see figure 13. in serial load mode, forty subsequent rising edges of w_clk will shift and load the 1-bit data on pin 25 (d7) through the 40-bit register in shift-register fashion. any further w_clk rising edges after the register is full will shift data out causing data that is left in the register to be out-of-sequence and cor rupt ed. the serial mode must be entered from the default parallel mode (see figure 17). data is loaded beginning with w0 and ending with w39. one note of caution: the 8-bit par al lel word (w0)xxxxx011that par al lel w o r d ( w 0 ) x x x x x 0 1 1 t h a t par al lel in vokes the serial mode should be overwritten with a valid 40-bit serial word im me di ate ly after entering the serial mode to prevent unintended engaging of the 6 refclk multiplier or entry into rev. d
ad9851 C14 C the fac to ry test mode. exit from serial mode to parallel mode is only possible using the reset command. the function assignments of the data and control words are shown in tables i and iii; the detailed timing sequence for up dat ing the output frequency and/or phase, resetting the de vice, engaging the 6 refclk multiplier, and powering up/down, are shown in the timing diagrams of figures 13 through 20. as a programming example for the following dds char ac ter is tics: 1. phase set to 11.25 2. 6 refclk multiplier engaged 3. powered-up mode selected 4. output = 10 mhz (for 180 mhz system clock) in parallel mode, user would program the 40-bit control word (composed of f ve 8-bit loads) as follows: w0 = 00001001 w1 = 00001110 w2 = 00111000 w3 = 11100011 w4 = 10001110 if in serial mode, load the 40 bits starting from the lsb lo ca tion of w4 in the above array, loading from right to left, and end ing with the msb of w0. table i. 8-bit parallel-load data/control word functional assignment word data[7] data[6] data[5] data[4] data[3] data[2] data[1] data[0] w0 phaseCb4 (msb) phaseCb3 phaseCb2 phaseCb1 phaseCb0 (lsb) power-down log ic 0 * 6 refclk multiplier enable w1 freqCb31 (msb) freqCb30 freqCb29 freqCb28 freqCb27 freqCb26 freqCb25 freqCb24 w2 freqCb23 freqCb22 freqCb21 freqCb20 freqCb19 freqCb18 freqCb17 freqCb16 w3 freqCb15 freqCb14 freqCb13 freqCb12 freqCb11 freqCb10 freqCb9 freqCb8 w4 freqCb7 freqCb6 freqCb5 freqCb4 freqCb3 freqCb2 freqCb1 freqCb0 (lsb) * this bit is always logic 0 unless invoking the serial mode (see figure 17). after serial mode is entered, this data bit must be set back to logic 0 for proper operation. w0 * w1 w2 w3 w4 t cd t dh t ds t wl t wh t fd t t t t t t fh fh fh fh fh t t t t t fl fl fl fl fl * output update can occur after any word load and is asynchronous with reference clock t t t t t cf cf cf cf cf cf valid dat a sysclk dat a w cl k fq ud a ou t figure 13. parallel load frequency/phase update timing sequence note: to update w0 it is not necessary to load w1 through w4. simply load w0 and assert fq_ud. to update w1, reload w0 then w1 users do not have random access to programming words. table ii. timing specif cations symbol def nition min t ds data setup time 3.5 ns t dh data hold time 3.5 ns t wh w_clk high 3.5 ns t wl w_clk low 3.5 ns t cd refclk delay after fq_ud 3.5 ns * t fh fq_ud high 7.0 ns t fl fq_ud low 7.0 ns t fd fq_ud delay after w_clk 7.0 ns t cf output latency from fq_ud frequency change 18 sysclk cycles phase change 13 sysclk cycles * specif cation does not apply when the 6 refclk multiplier is engaged. rev. d
ad9851 C15 C results of reset, figure 14 C phase accumulator zeroed such that the output = 0 hz (dc) C phase offset register set to 0 such that dac iout = full-scale output and ioutb = zero ma output C internal programming address pointer reset to w0 C power-down bit reset to 0 (power-down disabled) C 40-bit data input register is not cleared C 6 reference clock multiplier is disabled C parallel programming mode selected by default xxxxx10x fq ud w clk sysclk dac strobe data (w0) internal clocks disabled figure 15. parallel load power-down sequence/ internal operation xxxxx00x fq ud w clk data (w0) internal clocks enabled sysclk figure 16. parallel load power-up sequence (to recover from power-down)/internal operation entry to the serial mode, see figure 17, is via the parallel mode, which is se lect ed by default after a reset is asserted. one needs only to program the f rst eight bits (word w0) with the se quence xxxxx011 as shown in figure 17 to change from par al lel to serial mode. the w0 programming word may be sent over the 8-bit data bus or hardwired as shown in figure 18. after serial mode is achieved, the user must follow the programming se quence of figure 19. xxxxx011 fq ud w clk data (w0) enable serial mode figure 17. serial load enable sequence note: after serial mode is invoked, it is best to immediately write a valid 40-bit serial word (see figure 19), even if it is all zeros, fol lowed by a fq_ud rising edge to f ush the residual data left in the dds core. a valid 40-bit serial word is any word where w33 is logic 0. 28 27 26 25 1 2 3 4 ad9851 d3 d2 d1 d0 d4 d5 d6 d7 10k +v supply figure 18. hardwired xxxxx011 conf guration for serial load enable word w0 in figure 17 sysclk reset a ou t t rh t rl cos (0 ) symbol definition min spec t rh clk delay after reset rising edge 3.5n s * t rl reset falling edge after clk 3.5n s * t rr recovery from reset 2 sysclk cycles t rs minimum reset widt h 5 sysclk cycles t ol reset output latency 13 sysclk cycles * specifications do not apply when the ref clock multiplier is engage d t rr note: the timing diagram above shows the minimal amount of reset time needed before writing to the device. however, the master reset does no t have to be synchronous to the sysclk if the minimal time is not required. t rs t ol figure 14. master reset timing sequence note: the timing diagram above shows the minimal amount of reset time needed before writing to the device. however, the master reset does not have to be synchronous to the sysclk if the minimal time is not required. rev. d
ad9851 C16 C fq ud w2 data 40 40 w w clk cycles clk cycles w clk w1 w3 w3 9 w0 figure 19. serial load frequency/phase update sequence table iii. 40-bit serial load word functional assignment w0 freqCb0 (lsb) w1 freqCb1 w2 freqCb2 w3 freqCb3 w4 freqCb4 w5 freqCb5 w6 freqCb6 w7 freqCb7 w8 freqCb8 w9 freqCb9 w10 freqCb10 w11 freqCb11 w12 freqCb12 w13 freqCb13 w14 freqCb14 w15 freqCb15 w16 freqCb16 w17 freqCb17 w18 freqCb18 w19 freqCb19 w20 freqCb20 w21 freqCb21 w22 freqCb22 w23 freqCb23 w24 freqCb24 w25 freqCb25 w26 freqCb26 w27 freqCb27 w28 freqCb28 w29 freqCb29 w30 freqCb30 w31 freqCb31 (msb) w32 6 refclk multiplier en able w33 logic 0 * w34 power-down w35 phaseCb0 (lsb) w36 phaseCb1 w37 phaseCb2 w38 phaseCb3 w39 phaseCb4 (msb) * this bit is always logic 0. figure 20 shows a normal 40-bit serial word load sequence with w33 always set to logic 0 and w34 set to logic 1 or logic 0 to con trol the power-down function. the logic states of the re main ing 38 bits are unimportant and are marked with an x, indicating dont care status. to power down, set w34 = 1. to power up from a powered down state, change w34 to logic 0. wake-up from power-down mode requires approximately 5 s. note: the 40-bit input register of the ad9851 is fully pro gram - ma ble while in the power-down mode. fq ud w34 = 1 or 0 data (7) C 40 w_clk rising edges w clk w33 = 0 w35 = x w39 = x w38 = x w0 = x figure 20. serial load power-down\power-up sequence iout iout b v dd vinp / vinn v dd a. dac output c. comparator input digital out v dd digital in v dd b. comparator output d. digital input figure 21. i/o equivalent circuits rev. d
ad9851 C17 C pcb layout information the ad9851/cgpcb and ad9851/fspcb evaluation boards (figures 22 through 25 and tpcs 1 and 2) represent typical implementations of the ad9851 and exemplify the use of high frequency/high res o lu tion design and layout practices. the print- ed circuit board that contains the ad9851 should be a multilayer board that allows dedicated power and ground planes. the power and ground planes should (as much as possible) be free of etched traces that cause discontinuities in the planes. it is recommended that the top layer of the board also contain an interspatial ground plane that makes ground available without vias for the surface- mount devices. if separate analog and digital system ground planes exist, they should be con nect ed together at the ad9851 eval u a tion board for optimum per for mance. avoid running digital lines under the device as these will couple unnecessary noise onto the die. the power supply lines to the ad9851 should use as large a trace as possible to provide a low- impedance path and reduce the effects of switching currents on the power supply line. fast switching signals like clocks should use microstrip, controlled im ped ance techniques where pos- si ble. avoid crossover of digital and analog signal paths. traces on opposite sides of the board should run at right angles to each other. this will reduce crosstalk between the lines. good power supply decoupling is also an important con sid - er ation. the analog (avdd) and digital (dvdd) supplies to the ad9851 are independent and separately pinned out to min i mize coupling between analog and digital sections of the device. all analog and digital supply pins should be decoupled to agnd and dgnd, respectively, with high quality ceramic chip ca pac i tors. to achieve best performance from the decou- pling ca pac i tors, they should be placed as close as possible to the device. in systems where a common supply is used to drive both the avdd and dvdd supplies of the ad9851, it is rec- om mend ed that the systems avdd supply be used. analog devices applications engineering support is available to answer additional questions on grounding and pcb layout. call 1-800-analogd. evaluation boards two versions of the ad9851 evaluation board are available. the evaluation boards facilitate easy implementation of the device for bench-top analysis and serve as a reference for pcb layout. the ad9851/fspcb is intended for applications where the device will primarily be used as a frequency synthesizer. this version is optimized for connection of the ad9851 internal d/a converter output to a 50 spectrum analyzer input. the in ter nal comparator of the ad9851 is made available for use via wire hole access. the comparator inputs are externally pulled to opposing voltages to prevent comparator chatter due to f oating inputs. the dds dac output is unf ltered and no reference oscillator is pro- vided. this is done in recognition of the fact that many users may f nd an oscillator to be a liability rather than an asset. see figure 22 for an electrical schematic. the ad9851/cgpcb is intended for applications using the device as a cmos output clock generator. it connects the ad9851 dac output to the internal comparator input via a single-ended, 70 mhz low pass, 7th order, elliptic f lter. to minimize output jitter of the comparator, special attention has been given to the low-pass f lter design. primary considerations were input and output impedances (200 ) and a very steep roll- off characteristic to attenuate unwanted, nearby alias sig nals. the high impedance of the f lter allows the dac to de vel op 1 v p-p (with 10 ma) across the two 200 resistors at the input and output of the f lter. this voltage is entirely suf f cient to opti- mally drive the ad9851 comparator. this f lter was designed with the assumption that the ad9851 dds is at full clock speed (180 mhz). if this is not the case, f lter spec i f ca tions may need to change to achieve proper attenuation of an tic i pat ed alias signals. bnc connectors allow convenient ob ser va tion of the comparator cmos output and input, as well as that of the dac. no reference oscillator is provided for reasons stated above. this model allows easy evaluation of the ad9851 as a frequency and phase-agile cmos output clock source (see figure 24 for electrical schematic). jitter reduction note the ad9851/cgpcb has a wideband dds fundamental out put, dc to 70 mhz, and the on-chip comparator has even more band- width. to op ti mize low jitter performance users should con sid er band pass f ltering of the dac output if only a narrow band width is re quired. this will reduce jitter caused by spu ri ous, nonhar- monic signals above and below the desired signal. low er ing the ap plied v dd helps in re duc ing com par a tor switch ing noise by reducing v/ t of the com par a tor outputs. for op ti mum jitter per for mance, users should avoid the very busy digital en vi - ron ment of the on-chip com par a tor and opt for an external, high speed com par a tor. both versions of the ad9851 evaluation boards are designed to interface to the parallel printer port of a pc. the operating software (c++) runs under microsoft ? windows ? (windows 3.1 and windows 95); windows nt ? not supported and pro- vides a user-friend ly and intuitive format for controlling the functionality and ob serv ing the performance of the device. the 3.5-in disk provided with the evaluation board contains an executable f le that displays the ad9851 function-selection screen. the eval u a tion board may be operated with 3.0 v or 5 v sup plies. eval u a tion boards are conf gured at the factory for an external clock input. if the op tion al on-board crystal clock source is installed, resistor r2 (50 ) must be removed. evaluation board instructions required hardware/software personal computer operating in windows 3.1 or 95 en vi ron ment (does not support windows nt) printer port, 3.5-in f oppy drive, mouse, and centronics com- pat i ble printer cable, 3 v to 5 v voltage supply crystal clock oscillator or high frequency signal generator (sine wave output) with dc offset capability ad9851 evaluation board software disk and ad9851/fspcb or ad9851/cgpcb evaluation board setup copy the contents of the ad9851 disk onto the host pcs hard drive. (there are two f les, win9851.exe version 1.x and bwcc.dll.) connect the printer cable from the computer to the eval u a tion board. use a good quality cable as some cables do not connect every wire that the printer port supports. rev. d
ad9851 C18 C apply power to ad9851 evaluation board. the ad9851 is pow- ered separately from the other active components on the board via connector marked dut +v. the connector marked 5 v is used to power the cmos latches, optional crystal os cil la tor and pull-up resistors. both 5 v and dut +v may be tied together for ease of operation without adverse affects. the ad9851 may be powered with 2.7 v to 5.25 v. connect an external 50 z clock source or remove r2 and install a suitable crystal clock oscillator with cmos output levels at y1. a sine wave signal generator may be used as a clock source at frequencies >50 mhz by dc offsetting the output signal to 1/2 the supply voltage to the ad9851. this method requires a minimum of 2 v p-p signal and disabling of the 6 refclk multiplier function. locate the f le called win9851.exe and execute that program. the computer monitor should show a control panel that allows operation of the ad9851 evaluation board by use of a mouse. operation on the control panel locate the box labeled computer i/o. click the correct parallel printer port for the host com put er and then click the test box. a message will appear indicating whether the selection of output port is correct. choose other ports as necessary to achieve a correct port setting. click the master reset button. this will reset the part to 0 hz, 0 phase, parallel programming mode. the output from the dac iout should be a dc voltage equal to the full-scale output of the ad9851 (1 v for the ad9851/cgpcb and 0.5 v for the ad9851/fspcb), while the dac ioutb should be 0 v for both evaluation boards. reset should always be the f rst command to the ad9851 following power-up . locate the clock section and place the cursor in the frequency box. enter the clock frequency (in mhz) that will be applied to the reference clock input of the ad9851. click the pll box in the control function menu if the 6 reference clock multiplier is to be engaged a check mark will appear when engaged. when the reference clock mul ti pli er is en gaged, software will multiply the value entered in the fre- quen cy box by 6; otherwise, the value entered is the value used. click the load button or press the enter key. move the cursor to the output frequency box and type in the desired frequency (in mhz). click the load button or press the enter key. the bus monitor section of the control panel will show the 32-bit frequency word and 8-bit phase/ control word. upon completion of this step, the ad9851 output should be active at the programmed frequency/phase. changing the output phase is accomplished by clicking the down arrow in the output phase delay box to make a selection and then clicking the load button. note: clicking the load but- tons of the clock frequency box, the output frequency box, or the phase box will automatically initiate a re load ing of all three boxes and issuance of a fq_ud (fre quen cy update) pulse. to bypass this automatic reloading and fre quen cy update sequence, refer to the note below. other operational modes (frequency sweeping, sleep, serial input) are available. frequency sweeping allows the user to enter a start and stop frequency and to specify the frequency step size. sweeping begins at the start frequency, proceeds to the stop frequency in a linear manner, reverses direction, and sweeps back to the start frequency repeatedly. note: for those who may be operating multiple ad9851 eval- u a tion boards from one computer, a manual frequency update option exists. by eliminating the automatic issuance of an fq_ud, the user can load the 40-bit input registers of multiple ad9851s without transferring that data to the inter- nal accumulators. when all input registers are loaded, a single frequency update pulse can be issued to all ad9851s. a block diagram of this technique is shown in the ad9851 data sheet as a quadrature oscillator application. this single pulse synchronizes all the units so that their particular phases and frequencies take effect simultaneously. proper synchronization requires that each ad9851 be clocked by the same reference clock source and that each oscillator be in an identical state while being programmed. reset command ensures identical states. when manual frequency update is selected, a new box labeled frequency update will appear just above the frequency sweeping menu. clicking the box initiates a single fq_ud pulse. note: reset can be used to synchronize multiple oscillators. if several oscillators have already been programmed at various phases or frequencies, issuance of a reset pulse will set their outputs to 0 hz and 0 phase. by issuing a common fq_ud, the previously programmed information in the 40-bit input registers will transfer once again to the dds core and take effect in 18 clock cycles. this is due to the fact that reset does not affect the contents of the 40-bit input register in any way. the ad9851/fspcb provides access into and out of the on-chip comparator via test point pairs (each pair has an active input and a ground connection). the two active inputs are labeled tp1 and tp2. the unmarked hole next to each labeled test point is a ground connection. the two active outputs are labeled tp5 and tp6. adjacent to those test points are unmarked ground connec- tions. to prevent unwanted comparator chatter when not in use, the two inputs are pulled either to ground or +v via 1 k resistors. the ad9851/cgpcb provides bnc inputs and outputs as so - ci at ed with the on-chip comparator and an onboard, 7th order, 200 input /output z, elliptic 70 mhz low-pass f lter. jumper- ing (soldering a wire) e1 to e2, e3 to e4, and e5 to e6 connects the onboard f lter and the midpoint switching voltage to the comparator. users may elect to insert their own f lter and com- parator threshold voltage by removing the jumpers and inserting a f lter between j7 and j6 and providing a comparator threshold voltage at e1. use of the xtal oscillator socket on the evaluation board to sup- ply the clock to the ad9851 requires the removal r2 (a 50 chip resistor) unless the oscillator can drive a 50 load. the crystal oscillator should be either ttl or cmos (pref er a bly) compatible. rev. d
ad9851 C19 C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 9 8 7 6 5 4 3 2 12 13 14 15 16 17 18 19 11 1 strobe d0 d1 d2 d3 d4 d5 d6 d7 u2 74hct574 j1 c36cprx rrset 8d 7d 6d 5d 4d 3d 2d 1d 8q 7q 6q 5q 4q 3q 2q 1q ck oe ffqud wwclk check strobe 9 8 7 6 5 4 3 2 12 13 14 15 16 17 18 19 8d 7d 6d 5d 4d 3d 2d 1d 8q 7q 6q 5q 4q 3q 2q 1q ck oe 11 1 strobe reset wclk fqud check u3 74hct574 rreset wwclk ffqud rreset v cc y1 out gnd 7 8 14 5v xtal osc (optional) r2 50 j5 clkin remove when using y1 c2 0.1 f c3 0.1 f c4 0.1 f c5 0.1 f c8 0.1 f c9 0.1 f c10 0.1 f +v 5v c6 10 f c7 10 f +v 5v h1 #6 h2 #6 h3 #6 h4 #6 r3 2.2k strobe 5v wwclk ffqud rreset r8 2.2k r9 2.2k r10 2.2k j2 +v j3 +5v j4 gnd banana jacks 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 voutp vout n r set avdd agnd refclock fq ud d3 d2 d1 d0 w clk pvcc pgnd vinn vinp dacbp avdd agnd ioutb iout d4 d5 d6 d7 reset dvdd dgnd u1 ad9851 +v gnd clkin fqu d d3 d2 d1 d0 wclk +v gnd +v gnd d4 d5 d6 d7 rese t +v gnd r5 25 r4 50 gnd gnd tp1 tp3 tp2 tp4 r5 1k +v r7 1k gnd comparator inputs j6 dac out to 50 r1 3.9k gnd gnd tp5 tp6 tp7 tp8 10ma reset mounting holes ad9851/fspcb frequency synthesizer evaluation board nc nc = no connect figure 22. fspcb electrical schematic rev. d
ad9851 C20 C 23a. fspcb top layer 23b. fspcb power plane 23c. fspcb ground plane 23d. fspcb bottom layer figure 23. fspcb evaluation board 4-layer pcb layout patterns ad9851/fspcb evaluation board parts listgso 0516(a) miscellaneous hardware ref. des. 1 amp 552742-1, 36-pin plastic, right angle, pc mount, female j1 1 banana jack Ccolor not important j2 1 yellow banana jack j3 1 black banana jack j4 2 bnc coax. connector, pc mount j5, j6 1 ad9851/fspcb evaluation board gso 0516(a) none 4 amp 5-330808-6, open-ended pin socket none 2 #2-56 hex nut (to fasten j1) none 2 #2-56 3/8 binder head machine screw (to fasten j1) none 4 #4-40 hex nut (to fasten standoffs to board) none 4 #4 1-in metal stand-off none miscellaneous hardware ref. des. decoupling capacitors 7 size 1206 chip capacitor, 0.1 f c2Cc5, c8Cc10 2 tantalum capacitors, 10 f c6, c7 resistors 1 25 chip resistor, size 1206 r5 2 50 chip resistor, size 1206 r2, r4 1 3.9 k chip resistor, size 1206 r1 4 2 k or 2.2 k chip resistor, size 1206 r3, r8, r9, r10 2 1 k chip resistor, size 1206 r6, r7 integrated circuits 1 ad9851 direct digital synthesizer, surface-mount u1 2 74hct574an hcmos octal flip-flop, through-hole mount u2, u3 rev. d
ad9851 C21 C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 9 8 7 6 5 4 3 2 12 13 14 15 16 17 18 19 11 1 strobe d0 d1 d2 d3 d4 d5 d6 d7 u2 74hct574 j1 c36cpr2 rrset 8d 7d 6d 5d 4d 3d 2d 1d 8q 7q 6q 5q 4q 3q 2q 1q ck oe ffqud wwclk check strobe v cc y1 out gnd 7 8 14 5v xtal osc (optional) r2 50 j5 clkin remove when using y1 h1 #6 h2 #6 h3 #6 h4 #6 mounting holes r3 2.2k strobe 5v wwclk ffqud rreset r11 2.2k r9 2.2k r10 2.2k j2 +v j3 5v j4 gnd banana jacks 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 voutp voutn r set avdd agnd refclock fq ud d3 d2 d1 d0 w clk pvcc pgnd vinn vinp dacbl avdd agnd ioutb iout d4 d5 d6 d7 reset dvdd dgnd u1 ad9851 +v gnd clkin fqu d d3 d2 d1 d0 wclk +v gnd +v gnd d4 d5 d6 d7 reset +v gnd r5 100k r12 j7 bnc r1 3.9k 10ma reset c1 470pf e1 e2 r4 100k e6 e5 r6 200 c11 22pf c12 1pf l1 470nh c13 33pf c14 5.6pf l2 390nh c15 22pf c16 4.7pf l3 390nh c17 22pf r7 200 70mhz elliptical low-pass filter 7th order 200 z to bypass on board filter 1. remove e6 to e5 jumper 2. install appropriate r12 for iout termination r8 100 j6 e4 e3 j8 bnc j9 bnc 9 8 7 6 5 4 3 2 12 13 14 15 16 17 18 19 8d 7d 6d 5d 4d 3d 2d 1d 8q 7q 6q 5q 4q 3q 2q 1q ck oe 11 1 strobe reset wclk fqud check u3 74hct574 rreset wwclk ffqud rreset ad9851/cgpcb clock generator evaluation board (ssop package) c2 0.1 f c3 0.1 f c4 0.1 f c5 0.1 f c8 0.1 f c9 0.1 f c10 0.1 f +v 5v c6 10 f c7 10 f +v 5v nc nc = no connect figure 24. cgpcb electrical schematic rev. d
ad9851 C22 C 25a. cgpcb top layer 25b. cgpcb ground plane 25c. cgpcb power plane 25d. cgpcb bottom layer figure 25. fspcb evaluation board 4-layer pcb layout patterns rev. d
ad9851 C23 C cgpcb evaluation board parts listgso 0515(b) miscellaneous hardware ref. des. 1 amp 552742-1, 36-pin plastic, right angle, pc mount, female j1 1 banana jackcolor not important j2 1 yellow banana jack j3 1 black banana jack j4 5 bnc coax. connector, pc mount j5, j6, j7, j8, j9 1 ad9851/cgpcb evaluation board gso 0515(b) none 4 amp 5-330808-6, open-ended pin socket none 2 #2-56 hex nut (to fasten j1) none 2 #2-56 3/8 binder head machine screw (to fasten j1) none 4 #4-40 hex nut (to fasten stand-offs to board) none 4 #4 1-in metal stand-off #4 1-in metal stand-off #4 1-in metal stand-off none decoupling capacitors 1 size 1206 chip capacitor, 470 pf c1 7 size 1206 chip capacitor, 0.1 f c2Cc5, c8Cc10 2 tantalum capacitors, 10 f c6, c7 resistors 1 3.9 k chip resistor, size 1206 r1 1 50 chip resistor, size 1206 r2 4 2 k or 2.2 k chip resistor, size 1206 r3, r9, r10, r11 2 100 k chip resistor, size 1206 r4, r5 2 200 chip resistor, size 1206 r6, r7 1 100 chip resistor, size 1206 r8 1 dummy resistor (for optional installation) r12 filter capacitors (70 mhz 7-pole elliptic filter) 3 22 pf chip capacitor, size 1206 c11, c15, c17 1 1 pf chip capacitor, size 1206 c12 1 33 pf chip capacitor, size 1206 c13 1 5.6 pf chip capacitor, size 1206 c14 1 4.7 pf chip capacitor, size 1206 c16 inductors (70 mhz 7-pole elliptic filter) 1 470 nh chip inductor, coil craft 1008cs l1 2 390 nh chip inductor, coil craft 1008cs l2, l3 integrated circuits 1 ad9851 direct digital synthesizer, surface-mount u1 2 74hct574an hcmos octal flip-flop, through-hole mount u2, u3 rev. d
c00633C0C1/04(d) C24 C ad9851 outline dimensions 28-lead shrink small outline package [ssop] (rs-28) dimensions shown in millimeters 0.25 0.09 0.95 0.75 0.55 8 4 0 0.05 mi n 1.85 1.75 1.65 2.00 ma x 0.38 0.22 seating plane 0.65 bs c 0.10 coplanarit y 28 15 14 1 10.50 10.20 9.90 5.60 5.30 5.00 8.20 7.80 7.40 compliant to jedec standards mo-150ah revision history location page page 1/04data sheet changed from rev. c to rev. d renumbered f gures and tpcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . universal changes to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 updated ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 rev. d

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